More on Modulo 2n -1 Addition

Abstract : This brief paper describes an improvement of the FPGA implementation of the modulo (2^n-1) adder investigated in a previous research report.
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https://hal-lara.archives-ouvertes.fr/hal-02102102
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Submitted on : Wednesday, April 17, 2019 - 9:14:16 AM
Last modification on : Wednesday, November 20, 2019 - 2:51:42 AM

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  • HAL Id : hal-02102102, version 1

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Jean-Luc Beuchat. More on Modulo 2n -1 Addition. [Research Report] LIP RR-2003-14, Laboratoire de l'informatique du parallélisme. 2003, 2+2p. ⟨hal-02102102⟩

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