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Retiming DAGs

Abstract : The increasing complexity of digital circuitry makes global design optimization no longer possible: a designer will only consider the critical parts of his circuit. This paper discusses timing optimization problems when these critical parts can be represented by Direct Acyclic Graphs (DAGs). We deal with different (though related) clock period problems, under various external constraints. The main algorithm concerns the determination of the optimal clock period of a given circuit. We propose an efficient solution, based on the retiming technique, which improves current results in the literature. We give three different formulations depending on which combinational gates delay model is used: same delay for every gate, different delays or non-uniform delays.
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Submitted on : Wednesday, April 17, 2019 - 9:05:25 AM
Last modification on : Wednesday, October 26, 2022 - 8:14:49 AM


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  • HAL Id : hal-02101755, version 1



Pierre-Yves Calland, Anne Mignotte, Olivier Peyran, Yves Robert, Frédéric Vivien. Retiming DAGs. [Research Report] LIP RR-1995-18, Laboratoire de l'informatique du parallélisme. 1995, 2+20p. ⟨hal-02101755⟩



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