To Pin or Not to Pin: Asserting the Scalability of QEMU Parallel Implementation

M. Badaroux (1) , Saverio Miroddi (2) , Frédéric Pétrot (1)

1 TIMA-SLS - System Level Synthesis
2 Ticketsolve

Due to its speed in cross-executing sequential code, dynamic binary translation is the unchallenged technology for full system-level simulation. Among the translators, QEMU has become the de facto solution.  It introduced parallel host execution of the target cores a few years ago for the ARM instruction set architecture and this support is now also available, among others, for RISCV.  Given the popularity of these instruction sets in multi and many-core systems, assessing the scalability of their parallel implementation makes sense.  In this paper, we use a subset of the PARSEC benchmark to measure the execution time of QEMU's parallel implementation, to which we added the ability to pin a target processor to a host core or hardware thread.  We report the results of a wealth of experiments we performed on a 16-core/32-thread x86-64 SMP machine.  They show that the support of parallelism in QEMU scales well, and that, somewhat counter intuitively, pinning does not improve   performance.

Keywords: performance evaluation; discrete event simulation; dynamic binary translation; parallel simulation

Domains: Modeling and Simulation

M. Badaroux, Saverio Miroddi, Frédéric Pétrot. To Pin or Not to Pin: Asserting the Scalability of QEMU Parallel Implementation. 24th Euromicro Conference on Digital System Design (Euromicro DSD/SEAA 2021), Sep 2021, Palermo, Italy. pp.238-245, ⟨10.1109/DSD53832.2021.00045⟩. ⟨hal-03417343⟩