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Spiking Neuron Hardware-Level Fault Modeling

Abstract : The deployment of Artificial Intelligence (AI) hardware accelerators in a variety of applications, including safety-critical ones, requires assessing their inherent reliability to hardware-level faults and developing cost-effective fault tolerance techniques. This entails performing large-scale fault simulation experiments. However, transistor-level fault simulation is prohibitive and fault simulation should be carried out at a higher abstraction level. In this work, we focus on spiking neural networks (SNNs), and we follow a bottom-up approach starting from transistor-level simulations for developing a neuron behavioral-level fault model that can be readily employed for performing behavioral-level fault simulation of deep SNNs.
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Contributor : Haralampos Stratigopoulos <>
Submitted on : Thursday, June 18, 2020 - 11:47:04 AM
Last modification on : Friday, January 8, 2021 - 5:34:03 PM


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Sarah El-Sayed, Theofilos Spyrou, Antonios Pavlidis, Engin Afacan, Luis Camuñas-Mesa, et al.. Spiking Neuron Hardware-Level Fault Modeling. 26th IEEE International Symposium on On-Line Testing and Robust System Design, Jul 2020, Naples, Italy. ⟨10.1109/IOLTS50870.2020.9159745⟩. ⟨hal-02873418⟩



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