Parallel Execution of the Saturated Reductions

Benoît Dupont de Dinechin; Christophe Monat; Fabrice Rastello

Reports

Parallel Execution of the Saturated Reductions

Benoît Dupont de Dinechin ¹ Christophe Monat ¹ Fabrice Rastello ¹

1 LIP - Laboratoire de l'Informatique du Parallélisme

Abstract : This report addresses the problem of improving the execution performance of saturated reduction loops on fixed-point instruction-level parallel Digital Signal Processors (DSPs). We first introduce ``bit-exact'' transformations, that are suitable for use in the ETSI and the ITU speech coding applications. We then present ``approximate'' transformations, the relative precision of which we are able to compare. Our main results rely on the properties of the saturated arithmetic.

Keywords : ETSI / ITU Speech Coding Fixed-Point Arithmetic Fractional Arithmetic Instruction Level Parallelism Parallel Reductions Saturated Reductions

Document type :

Reports

Domain :

Computer Science [cs]

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https://hal-lara.archives-ouvertes.fr/hal-02101824
Contributor : Colette Orange <>
Submitted on : Wednesday, April 17, 2019 - 9:07:15 AM
Last modification on : Saturday, September 11, 2021 - 3:19:19 AM

Parallel Execution of the Saturated Reductions

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Parallel Execution of the Saturated Reductions

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