Coordinating the fetch and issue warp schedulers to increase the timing predictability of GPUs

Noïc Crouzet (1) , Thomas Carle (1) , Christine Rochange (1)

1 IRIT-TRACES - Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués

The verification of a time-critical system requires precise analysis of execution times, which makes assumptions on the system's behavior, especially when it is poorly documented. One of those assumptions, when the system features a GPU accelerator, relates to the policy that each Streaming Multiprocessor (SM) follows to schedule warps. We argue that the literature overlooks the lack of synchronization between the instruction fetch and instruction issue schedulers, while this is likely to make the behavior of existing GPUs unpredictable. We propose to coordinate the action of the fetch and issue stages in GPU pipelines in order to enable reliable static timing analysis. We implement our approach in Vortex, a RISC-V-based open-source GPU. We report experiments that show that it makes warp scheduling predictable with little performance costs.

Keywords: RISC V; GPU; real time; timing predictability; warp scheduling

Domains: Computer Science [cs]

Noïc Crouzet, Thomas Carle, Christine Rochange. Coordinating the fetch and issue warp schedulers to increase the timing predictability of GPUs. Euromicro Symposium on Digital System Design, Aug 2024, Paris, France. ⟨hal-04729449⟩