Multi-core interference over-estimation reduction by static scheduling of multi-phase tasks

Rémi Meunier (1, 2, 3, 4) , Thomas Carle (1) , Thierry Monteil (2)

1 IRIT-TRACES - Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués
2 IRIT-SEPIA - Système d’exploitation, systèmes répartis, de l’intergiciel à l’architecture
3 AUSY
4 INSA Toulouse - Institut National des Sciences Appliquées - Toulouse

Interference between tasks running on separate cores in multi-core processors is a major challenge to predictability for real-time systems, and a source of over-estimation of worst-case execution duration bounds. This paper investigates how the multi-phase task model can be used together with static scheduling algorithms to improve the precision of the interference analysis. The paper focuses on single-period task systems (or multi-periodic systems that can be expanded over an hyperperiod). In particular, we propose an Integer Linear Programming (ILP) formulation of a generic scheduling problem as well as 3 heuristics that we evaluate on synthetic benchmarks and on 2 realistic applications. We observe that, compared to the classical 1-phase model, the multi-phase model allows to reduce the effect of interference on the worst-case makespan of the system by around 9% on average using the ILP on small systems, and up to 24% on our larger case studies. These results pave the way for future heuristics and for the adoption of the multi-phase model in multi-core context.

Keywords: Multi-core WCET Interference Static scheduling; Multi-core; WCET; Interference; Static scheduling

Domains: Hardware Architecture [cs.AR]; Embedded Systems

Rémi Meunier, Thomas Carle, Thierry Monteil. Multi-core interference over-estimation reduction by static scheduling of multi-phase tasks. Real-Time Systems, 2024, pp.1--39. ⟨10.1007/s11241-024-09427-3⟩. ⟨hal-04689317⟩